The Design and Implementation of Low Power Digital FIR Filter In 90 nm CMOS Technology

Abstract

Digital Finite Impulse Response (FIR) filtering is used to produce digital output by taking digital input. Digital filtering is one of the most powerful tools of digital signal processing. In Very Large-Scale Integration (VLSI) technology the usage of Digital Signal Processor (DSP) in FIR filter plays important role in various signal processing. The aim of this project is to have the best power consumption in the design of FIR filter integrated circuits for reasons of portability, miniaturization, and energy conservation. In this project, the design of adder and multiplier circuits for the FIR filters that have the best power consumption is very critical. A custom full adder utilizing the hybrid method and Vedic multiplier using 90 nm Complementary Metal Oxide Semiconductor (CMOS) technology is proposed. By employing the hybrid full adder (HFA) along with the Vedic algorithm, a 3-tap FIR circuit in direct form structure is designed using Cadence EDA tools. With this method, the number of transistors in the adder and multiplier circuits for the FIR filter circuit is less, thus it improves the power consumption of the system. The power consumption for the 4x4-bit Vedic multiplier is 0.212 mW at a supply voltage of 1.0 V.