The Design and Implementation of Low-Power 4-bit Reversible Multiplier
Keywords:Reversible Logic Gate , Reversible Logic Circuit, Reversible Multiplier, Power Consumption
Most processors operating using irreversible logic had wasted a significant amount of energy. Most of this is coming while performing the arithmetic operation and one of the operations is the multiplier. A fast multiplier is needed since slow multiplication can affect the performance of the processors. Hence, reversible logic can be implemented to solve the energy wastage and performance issues in the multiplier. Reversible logic has been brought out to be an optimistic computing model having applications in low power Complementary Metal Oxide Semiconductor (CMOS), nanotechnology, quantum computing, and deoxyribonucleic acid (DNA) computing. This project has investigated the power consumption and speed efficiency of a 4-bit reversible multiplier. The multiplier is based on the Wallace architecture and uses the Peres gate as the reversible logic gate. The circuit is designed using Mentor Graphics with 130 nm and 180 nm CMOS technology and the supply voltage is at 1 V and 1.2 V. It is found that the power consumption for the reversible multiplier circuit using 130 nm and 1 V is 583.35 µW while for 1.2 V, it is 1.0853 mW. As for the speed, the reversible multiplier is 27.5% faster than the conventional multiplier where the average delay is 69.48 ps. In conclusion, it can be said that a reversible multiplier is better than a conventional multiplier.