VLSI Implementation of Low Power Face Detection System
Keywords:face detection system, low power, VLSI
This study explores the implementation of a face detection system utilizing Very Large Scale Integration (VLSI) method in improving the low power requirement of the system. Previously, the focus of VLSI was on the area constraints and timing. However, power consumption was becoming more important when the equipment density increases dramatically. When the threshold voltage decreases, the leakage current increases. High power consumption can cause various problems, such as increasing product cost, reducing reliability and reducing battery life. With the help of Electronic Design Automation (EDA) tools, circuits with low power consumption can be designed and at the same time minimized the area. This study is focused on VLSI design flow from Register-Transfer Level (RTL) to Graphic Database System II (GDSII). The EDA tools used in this project are Synopsys Design Compiler and Synopsys IC Compiler from logic synthesis to verification process. Power consumption is improved by using a clock gating technique and the design is optimized after the process. The design has passed the design verifications such as timing, area and power and fulfill the objectives of the study.