Smart Traffic Light Controller for UTHM Main Entrance
Keywords:Smart Traffic Light, Controller System, IR Sensors
A traffic light controller (TLC) system is used to safely control vehicles' movement on the road to avoid collisions happened especially at intersections. Traffic lights control traffic movement by allocating adequate time between users from different intersections in the area. Usually, all traffic lights on the major roads are controlled by a fixed-time control system, while the minor roads are controlled independently by sensors. This project aims to create an efficient traffic light controller system to manage T-junction roads' movement at the UTHM main entrance and to ensure optimum traffic use. During peak hours, when people go out or come back home, traffic is at the maximum capacity, and without an efficient TLC system, it always happened to be jammed. The problem arises due to the unbalanced traffic flow from the exit road of UTHM, which has fewer vehicles most of the time, but it can also be the most congested road, especially during peak hours. The existed TLC system cannot configure the jam level in any way. To solve this problem, this designed controller system, used infrared sensors to detect the presence of vehicles and also to detect the traffic condition by placing sensors at the minor roads. The level of traffic density on the minor road is determined by placing three sensors at a different point, in this case, the exit way of UTHM campus. The first sensor indicates normal traffic, the second sensor indicates medium traffic, and the third sensor indicates heavy traffic. The timers are set according to the jam levels, which will indirectly help drivers save their time on the road. This controller system is able to detect level of traffic density as well as promotes efficient waiting time for drivers. The results of this controlled system are obtained from ModelSim. Various test bench has been made to verify the functionality and performance of the controller system through simulation. The controller system is described in Verilog HDL using Altera Quartus II.