Hardware Implementation of a Cryptographic Coprocessor

Abstract

The purpose of this project is to design the hardware of the cryptographic coprocessor by using Verilog Hardware Description Language (HDL). Cryptographic coprocessor has been widely used to offload the compute-intensive cryptography tasks from the main processor due to its performance and efficiency compared to the pure software solution. The proposed coprocessor comprises an input register, 16x16 register files, instruction decoder, control unit, arithmetic logic unit (ALU) and the hashing unit. The hashing unit is implemented using a non-linear look-up table (LUT). The instruction set architecture (ISA) consists of 12 instructions that execute independently from the main processor. The 16-bit hash circuit provides a faster way of implementing a hash function for any cryptographic algorithms as compared to software implementation. The design is simulated to verify the functionality of the proposed ISA using the ModelSim Intel Field Programmable Gate-Array (FPGA). Simulation results show that the proposed cryptographic coprocessor produces the correct outputs as in specifications.