Design of 32-Bit RISC-V Architecture Using Verilog Hardware Description Language

Abstract

RISC-V architecture is an open standard instruction set architecture that is established based on of RISC architecture. The RISC-V architecture is an open source, free, user-friendly access, and easy to modify. RISC-V offers a reduced instruction set that is lightweight and modular. Thus, its architecture is less complex and easy to be customised. Hence, this paper presents the design and development of a 32-bit RISC-V processor architecture from fundamental concepts, encompassing instruction set definition, datapath design and control logic implementation. Verilog HDL language is used to design the architecture that comprises combination of behavioural modelling and structural modelling structure. The processor is designed based on the RV32I instruction set where the key components include Program Counter, Instruction Memory, Register File, ALU, Immediate Generator, Data Memory, Branch Comparator, Multiplexer and Control Unit. The design is expected to perform operations for instruction types of R, I, B, S, U and J. Eleven instructions were chosen for the implementation and validation. The functionality of the design was tested using ModelSim-Altera, to ensure the architecture able to produce the desired results. After the functional test, a timing performance analysis is conducted to ensure that the processor meets the time requirements. The simulation results indicate that the designed architecture able to produce correct results for all the selected operations. In addition, the timing analysis shows that the processor can operate with a maximum operating frequency of 40.88 MHz. As conclusion, the processor met all the design objectives and functions as expected. For future improvement, it is recommended to extend the work with FPGA prototyping and pipelining structure to improve throughput performance. By doing so, the research could move from theory to real-world application, making the processor more reliable and handle more instructions per cycle, reducing delays and improving processing speed.