FPGA Implementation of BLDC Motor Control

Abstract

Permanent Magnet Brushless DC (BLDC) motors are widely used in industries like electric bicycles, industrial robots, and CNC welding machines. Due to the efficient electronic control system and compact design, they have become a key component in the automation industry. However, they face significant problems when obtaining accurate motor movement and performing speed control. This work concentrates on designing a BLDC motor control system and generating hardware architecture design using PWM and PID controller. The performance of the BLDC motor control in terms of hardware implementation and optimization effects on the target FPGA device was evaluated. This work used Simulink from MATLAB software for motor control circuit design and Vivado software for performance verification on the Zynq-7000 target devices. Hardware control system performance, which includes power consumption, clock speed, and utilization of HDL, is being evaluated in this work. Simulink MATLAB is also used to construct the entire control system process for optimization and generate the VHDL code using the HDL coder from the designated block diagram. Vivado software is used to verify Simulink's simulation and analyze the HDL optimization by implementing it on the target FPGA device. The results show the comparison between modeling simulation on Simulink and Vivado regarding the generated output waveform and the hardware architecture design performance after enabling various optimization options. Both simulation outcomes validate the effectiveness of utilizing Simulink MATLAB for circuit diagram design and HDL code generation. The evaluated performance of on-chip power consumption is enhanced by 47% and 90% faster than the non-optimization option regarding the clock speed. Worst Negative Slack (WNS) for pipelining and resource sharing is 95% better than the Baseline option.