Characterization of a 0.14 Î¼m Submicron NMOS with Silvaco TCAD Simulator
Keywords:sidewall spacer, LDD, retrograde well, metallization
A 0.14 μm NMOS was simulated using ATHENA and ATLAS modules from TCAD simulator. The electrical characteristics of the submicron device were studied. Constant field scaling was applied to the following parameters: the effective channel length, the density of the ion implantation for threshold voltage (VTH) adjustment, and the gate oxide thickness (TOX). Additional techniques implemented to avoid short channel effects in submicron devices were shallow trench isolation (STI), sidewall spacer deposition, lightly doped drain (LDD) implantation, and retrograde well implantation. The results show that retrograde well implantation allowed the highest density of the dopant to fall below the surface of the substrate. With the application of sidewall spacer and LDD implantation, a lighter doped region was created beyond the n+ drain/source junction. As the layers of metallization increases, it was observed that drain current (ID) increased as well. The important parameters for NMOS were measured and validated.
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