Ultralow-Power and Secure S-Box Circuit Using FinFET Based ECRL Adiabatic Logic

  • Srilakshmi Kaza Gudlavalleru Engineering College
  • A. V. N. Tilak Gudlavalleru Engineering College
  • K. Srinivasa Rao TRR College of Engineering
Keywords: Cyber Security, Low-power, ECRL, FinFET, PPRM, S-box

Abstract

Advanced Encryption Standard (AES) is the widely used technique in critical cyber security applications. In AES architecture S-box is the most important block. However, the power consumed by      S-box is 75% of the total AES design. The   S-box is also prone to Differential Power Analysis (DPA) attack which is one of the most threatening types of attacks in cryptographic systems. In this paper, a     three-stage positive polarity Reed-Muller (PPRM) S-box is implemented with 45nm FinFET using Efficient Charge Recovery Logic (ECRL) to reduce power consumption. The simulation results indicate up to 66% power savings for FinFET based S-box as compared to CMOS design. Further, the FinFET ECRL 8-bit     S-box circuit is evaluated for transitional energy fluctuations and peak current traces to compare its resistance against side-channel attacks. The lower energy variations and uniform current trace exhibit the improved security performance of the circuit to withstand DPA and Differential Electromagnetic Radiation Attacks (DEMA).

Author Biography

Srilakshmi Kaza, Gudlavalleru Engineering College
ELECTRONICS AND COMMUNICATION ENGINEERING
Published
2018-09-19
How to Cite
Kaza, S., Tilak, A. V. N., & Srinivasa Rao, K. (2018). Ultralow-Power and Secure S-Box Circuit Using FinFET Based ECRL Adiabatic Logic. Journal of Science and Technology, 10(3). Retrieved from https://publisher.uthm.edu.my/ojs/index.php/JST/article/view/2525