Efficient Implementation of Searchless Fractal Image Compression on Low-cost FPGA for Real-Time Encoding

Abstract

Self-similarity within images is utilized by Fractal Image Compression (FIC) method to provide potential benefit of high compression ratio, good recovery performance, flexible recovery resolution, and fast decoding process. Nevertheless, FIC suffers from a major drawback, that is its time-consuming operation, especially when a full search is attempted. It poses challenges to achieve a real-time compression. In this paper, a real-time hardware architecture is proposed for encoding images with searchles-based FIC method. The proposed design encoded the image blocks in different sizes based on quadtree approach. The design is synthesized and implemented on a low-cost FPGA, and it is optimized at the circuit level through parallelism and pipelining to achieve a real-time encoding. The performance of the proposed design is quantitatively evaluated in terms of encoding time, resource usage, peak-signal-to-noise-ratio (PSNR) and compression ratio. With an operating frequency of 50 MHz, a run time of 9.65 ms can be achieved for an 512×512×8 image, which is equivalent to 103 images which can be encoded per second. The design consumes less than half of the total device resource in the low-cost Cyclone V SoC FPGA. The average PSNR and compression ratio achieved are  32 dB and 14:1 respectively.