Low Leakage Low Power Domino Logic Technique for Wide Fan-In Applications, 40-Bit Tag Comparator

Domino based TAG Comparator

Abstract

Advances in sub-micron technologies make low power consumption and delay a major concern for present day systems. These parameters play a critical role in the performance of most widely used wide fan-in- dynamic logic gates. These wide fan-in dynamic gates are employed in designing high speed tag comparators which are critical blocks of cache memory. The proposed technique tries to have an insight on a 40-bit tag comparator in terms of power consumption and noise immunity to produce a high performance logic style. The approach limits the voltage swing at the dynamic node with the help of stack transistor employed between dynamic node and clocked bleeder transistor. This technique will reduce the overall power consumption and improves the gate speed for constant noise immunity. The observation is carried out with 1 GHz clock frequency and 0.9 V supply at 27 ⁰C temperature using Cadence Virtuoso Spectre and Layout editor for 90 nm CMOS technology