7-level of Asymmetric MLI with Reduced Number of Switching Devices Structure for High Power-Density Achievement Using Pareto-Front Method

Abstract

In order to obtain high power density utilizing the Pareto-Front technique, this study presents the performance of the suggested 7-level asymmetric multilevel inverter (AMLI) topology employing a reduced number of switching devices (RNSD) structure. In order to decrease total harmonic distortion (THD), AMLI topology primarily produces greater levels of output voltage without changing the structure. For a 7-level AMLI, a 5-level RNSD structure is suggested as the circuit configuration. The suggested circuit construction will be operated using the sinusoidal pulse width modulation (SPWM) switching strategy. In actuality, because SPWM generates the switching scheme using a sine wave as a reference, its THDs are smaller than those of PWM. In accordance with IEEE Std 519-1992, the LC passive filter is taken into consideration. It demonstrates that the THD of the 7-level AMLI is the lowest in simulation, at 0.8%, compared to 4.4% in experimental data. The Pareto-Front method comparison results showed that, despite the switching frequency changing from 2 kHz to 500 kHz, the proposed 7-level AMLI with RNSD structure is still able to achieve high efficiency at 98.52% and high power-density of 4.46 kW/dm3 at 75 kHz when compared to the 7-level cascaded H-bridge structure.