A Novel Hybrid Full Adder using 13 Transistors

Authors

  • Lee Shing Jie Universiti Tun Hussein Onn Malaysia, 86400 Johor, MALAYSIA
  • Siti Hawa Ruslan Universiti Tun Hussein Onn Malaysia, 86400 Johor, MALAYSIA

Keywords:

Adder, Hybrid design, Sum circuit, Low power

Abstract

Full adder is a basic and vital building block for various arithmetic circuits such as multipliers. In this paper, a hybrid 1-bit full adder using complementary metal-oxide semiconductor (CMOS) logic style had been designed. This hybrid adder divided into three modules. Module I is a three transistors XOR gate. Module II is a novel sum circuit which successfully modified with the usage of lesser number of transistors used. Module III is a carry circuit which uses the carry output of module I and several other input to generate carry output. Performance parameters such as power and delay were compared to some of the existing designs. With a 1.8V voltage supply, the average power consumption of proposed hybrid adder was found extremely low which is 2.09 μW and a very low delay of 350 ps. Design in both speed and energy consumption becomes even more significant as the word
length of the adder increases. The full adder design is simulated using Tanner EDA version 16 using General Process Design Kit (GPDK) 250nm technology CMOS processes.

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Author Biographies

Lee Shing Jie, Universiti Tun Hussein Onn Malaysia, 86400 Johor, MALAYSIA

Department of Electrical and Electronic Engineering, Faculty of Electric & Electronic Engineering

Siti Hawa Ruslan, Universiti Tun Hussein Onn Malaysia, 86400 Johor, MALAYSIA

Department of Electrical and Electronic Engineering, Faculty of Electric & Electronic Engineering

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Published

01-04-2016

How to Cite

Shing Jie, L., & Ruslan, S. H. (2016). A Novel Hybrid Full Adder using 13 Transistors. International Journal of Integrated Engineering, 8(1). Retrieved from https://publisher.uthm.edu.my/ojs/index.php/ijie/article/view/1400

Issue

Section

Issue on Electrical and Electronic Engineering