Temperature Variation Operation of Mixed-VT 3T GC-eDRAM for Low Power Applications in 2Kbit Memory Array

Authors

  • Hussien Abdo Technische Universität Kaiserslautern
  • N. Ezaila Alias Universiti Teknologi Malaysia
  • Afiq Hamzah Universiti Teknologi Malaysia
  • Izam Kamisian Universiti Teknologi Malaysia
  • M. L. Peng Tan
  • U. Ullah Sheikh

Keywords:

GC-DRAM, embedded memories, DRT, leakage

Abstract

Embedded memories were once utilized to transfer information between the CPU and the main memory. The cache storage in most traditional computers was static-random-access-memory (SRAM). Other memory technologies, such as embedded dynamic random-access memory (eDRAM) and spin-transfer-torque random-access memory (STT-RAM), have also been used to store cache data. The SRAM, on the other hand, has a low density and severe leakage issues, and the STT-RAM has high latency and energy consumption when writing. The gain-cell eDRAM (GC-eDRAM), which has a higher density, lower leakage, logic compatibility, and is appropriate for two-port operations, is an attractive option. To speed up data retrieval from the main memory, future processors will require larger and faster-embedded memories. Area overhead, power overhead, and speed performance are all issues with the existing architecture. A unique mixed-V_T 3T GC-eDRAM architecture is suggested in this paper to improve data retention times (DRT) and performance for better energy efficiency in embedded memories. The GC-eDRAM is simulated using a standard complementary-metal-oxide-semiconductor (CMOS) with a 130nm technology node transistor. The performance of a 2kbit mixed-V_T 3T GC-eDRAM array were evaluated through corner process simulations. Each memory block is designed and simulated using Mentor Graphics Software. The array, which is based on the suggested bit-cell, has been successfully operated at 400Mhz under a 1V supply and takes up almost 60-75% less space than 6T SRAM using the same technology. When compared to the existing 6T and 4T ULP SRAMs (others' work), the retention power of the proposed GC-eDRAM is around 80-90% lower.

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Published

22-06-2022

How to Cite

Abdo, H., Alias, N. E., Hamzah, A., Kamisian, I., Tan, M. L. P., & Sheikh, U. U. (2022). Temperature Variation Operation of Mixed-VT 3T GC-eDRAM for Low Power Applications in 2Kbit Memory Array. International Journal of Integrated Engineering, 14(3), 193–201. Retrieved from https://publisher.uthm.edu.my/ojs/index.php/ijie/article/view/10273