A 4x4 Bit Vedic Multiplier with Different Voltage Supply in 90 nm CMOS Technology - Lee, Shing Jie; Ruslan, Siti Hawa (International Journal of Integrated Engineering, 2017)
In recent years, due to the rapid growth of high performance digital systems, speed and power consumption become very vital in multiplier design. In this paper, a 4x4 bit Vedic multiplier has been designed using the combination of Urdhva Triyakbyam Sutra and 13T hybrid full adder (HFA). This algorithm satisfied the requirement of a fast multiplication operation because of the vertical and crosswise architecture from the Urdhva Triyakbyam Sutra which minimize the number of partial products compared to the conventional multiplication algorithm. The multiplier is simulated using Synopsys Custom Tools with General Process Design Kit (GPDK) of 90 nm CMOS technology using several voltage supplies to find the most optimum value for the voltage supply to be used. The result shows that with the usage of 1 V voltage supply, the new design of multiplier using a combination of HFA and Vedic mathematics is able to produce the lowest power consumption and least delay time. The 4x4 bit Vedic multiplier is able to yield a full output voltage swing with a power consumption of only 0.2015 mW, delay of 376 ps and compact area of 3100 Âµm2.